There are two ways of using titanium silicide in Si-based devices: polycide gate electrode/interconnect and contact/interconnect in self-aligned silicide (SALICIDE) process. This chapter will first ...

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use with host, embedded host, On-the-Go (OTG) ...

In order to reduce the parasitic resistances in scaled CMOS transistors, self-aligned silicide (salicide) [2] technologies have been developed. Although titanium (Ti) silicide was used for 0.35 0.18 ...

Also include support for AVS busses. Supported multiple ... VeriSilicon SMIC 0.18um 1.8V/3.3V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International ...